1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a method for fabricating a bipolar transistor that improves a fast characteristic of the transistor at low operating voltages.
2. Background of the Related Art
Generally, the fast characteristic of a semiconductor device is very important if the device is used in a high frequency semiconductor circuit. To achieve a fast characteristic, prior methods have reduced the size of the semiconductor device. To reduce the size of the semiconductor device, related art methods have been provided for selectively forming an epitaxial layer and a floating poly base. Such methods are intended to reduce junction capacitance between a base and a collector in a bipolar transistor, and also to reduce parasitic capacitance between them by forming a thick insulating film on the bottom of a floating poly base.
A related art method for fabricating a bipolar transistor will be described with reference to the accompanying drawings.
FIG. 1a to FIG. 1i are sectional views illustrating process steps of a related art method for fabricating a bipolar transistor. As shown in FIG. 1a, an N.sup.+ conductive type buried layer 13 is formed in a P conductive type semiconductor substrate 11. A first oxide film 15 is formed on an entire surface of the semiconductor substrate 11 including the buried layer 13. A first polysilicon layer 17 is formed on the first oxide film 15.
Subsequently, as shown in FIG. 1b, a photoresist 19 is deposited on the first polysilicon layer 17 and then patterned by exposure and developing processes. The first polysilicon layer 17 is selectively removed by an etching process using the patterned photoresist 19 as a mask to form a floating poly base 17a. The first oxide film 15 is formed thick to reduce parasitic capacitance between the floating poly base 17a and the buried layer 13.
As shown in FIG. 1c, a first chemical vapor deposition (CVD) oxide film 21 is deposited on the entire surface of the semiconductor substrate 11, including the floating poly base 17a. A photoresist (not shown) is then deposited on the first CVD oxide film 21 and patterned by exposure and developing processes. The first CVD oxide film 21, the floating poly base 17a, and the first oxide film 15 are sequentially removed by an etching process using the patterned photoresist as a mask to define a first region and a second region. At this time, a surface of the buried layer 13 is exposed.
As shown in FIG. 1d, a second CVD oxide film is deposited on the entire surface of the semiconductor substrate 11, including the first CVD oxide film 21, and then etched back to form a first sidewall 23 on inner walls of the first and second regions. Thereafter, a first epitaxial layer 25 is epitaxially grown by using the buried layer 13 as a seed.
As shown in FIG. 1e, the first sidewall 23, which is formed on the sides of the floating poly base 17a and the first CVD oxide film 21 in the first and second regions, is partially removed. As shown in FIG. 1f, the first epitaxial layer 25 in the first and second regions is used as a seed to epitaxially grow a second epitaxial layer 27 having the same height as the floating poly base 17a.
As shown in FIG. 1g, a buffer oxide film 29 is grown on the second epitaxial layer 27 in the first and second regions. The buffer oxide film 29 serves as a buffer during ion implantation. P conductive type impurity ions are implanted into the second epitaxial layer 27 in the first region and N.sup.+ conductive type impurity ions are implanted into the second epitaxial layer 27 in the second region. Then, the second epitaxial layer 27 in the first region is used as a base and the second epitaxial layer 27 in the second region is used as a collector contact region. Subsequently, a third CVD oxide film 31 is formed on the entire surface of the semiconductor substrate 11 including the second epitaxial layer 27.
As shown in FIG. 1h, the third CVD oxide film 31 is etched back to form a second sidewall 31a on the sides of the first CVD oxide film 21. The buffer oxide film 29 is then etched using the second sidewall 31a as a mask to expose the second epitaxial layer 27 in the first region, into which the P conductive type impurity ions are implanted.
As shown in FIG. 1i, a second polysilicon layer is formed on the entire surface of the semiconductor substrate 11 including the exposed second epitaxial layer 27. The second polysilicon layer is then selectively removed to form an emitter poly 33 which contacts the epitaxial layer 27 in the first region. The emitter poly 33 includes polysilicon that is doped with impurities. The impurities are diffused into the second epitaxial layer 27 so that emitter junction 33a is formed. Subsequently, the first CVD oxide film 21 is selectively removed to expose the surface of the floating poly base 17a on both sides of the second epitaxial layer 27. A metal is deposited on the entire surface and then patterned to form an electrode pattern 35. This completes the related art method for fabricating a bipolar transistor.
As discussed above, the related art method for fabricating a bipolar transistor selectively grows the epitaxial layer and the floating poly base to reduce the junction capacitance between the base and the collector. The related art method also reduces parasitic capacitance between the base and the collector by forming a thick insulating film on the bottom of the floating poly base.
However, the related art method for fabricating a bipolar transistor has several problems. One problem is that the thickness of the epitaxial layer is the same as the thickness of the thick insulating film formed on the bottom of the floating poly base. The unnecessarily thick epitaxial layer reduces the fast characteristics of the semiconductor device during low voltage operation.